NU 2016-087

Inventors

Jie Gu*

Russ Joseph

Short Description

A technique that lowers power consumption without sacrificing the speed of a microprocessor

Abstract

The conventional microprocessor design has reached a bottleneck on improvement, i.e. it is very difficult to reduce power without trading off performance. Northwestern researchers propose a novel technique to achieve further energy saving without sacrificing performance. By collaborating on-chip regulator or clock generation circuitry with the fetched instructions in the pipeline stages, they can allow chip voltage to scale automatically based on the need from the instructions under operation. The key techniques that enable the instruction governed operation includes (1) an analysis methodology to create a sophisticated mapping of hardware critical path and software instruction; (2) an integrated voltage regulator or clock generator operation scheme controlled by instruction types; and (3) a compiler optimization methodology to improve the energy efficiency in the proposed scheme. This technology allows chip venders to achieve lower power consumption which is critical issue for modern chip's operation.

Applications

• Low Power and High performance Microprocessor Design
• Low Power Digital Signal Processing (DSP) Circuit Design
• Embedded Integrated Circuits (ICs) used in Wearable Electronics or Medical Devices

Advantages

• Significant energy savings: Utilizes single instruction level voltage & frequency scaling vs conventional counterpart which requires tens of thousands to millions of instruction

Publications

Jia T, Fan Y, Joseph, R and Gu J (2016). Exploration of associative power management with instruction governed operation for ultra-low power design. In Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. (Vol. 05-09-June-2016)

IP Status

Provisional patent application has been filed.